1. Field of the Invention
The invention generally relates to semiconductor memory devices and, more particularly, to a memory programming and erase method and device with optimal data retention for a nonvolatile memory.
2. Description of the Related Art
Memory devices for nonvolatile storage of information are commonly available in the art. Exemplary nonvolatile semiconductor memory devices include read only memory (ROM), flash memory, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and electrically erased. Flash EEPROMs further include the additional capability of erasing all memory cells therein at once. The common use of EEPROM semiconductor memory has prompted the development of an EEPROM memory cell with optimal performance characteristics, e.g., shorter programming times, lower voltage usage for programming and reading, longer data retention time, shorter erase time, smaller and miniaturized physical dimensions.
FIG. 1 is a block diagram that illustrates the structure of a prior art nonvolatile memory cell where a nonvolatile memory cell 70 includes an N-channel MOSFET structure. The nonvolatile memory cell 70 includes a P type substrate 706 with two buried N+ junctions, one being source 700 and the other being drain 701. A channel 707 is formed between the source 700 and the drain 701. Above the channel 707 is a first isolating layer 703, which generally is a silicon oxide layer. On top of the first isolating layer 703 is a trapping layer 704, which generally is a nitride layer. The trapping layer 704 forms the memory retention layer that traps the hot electrons as they are injected into the nitride layer. A second isolating layer 705, which generally is an oxide layer, is formed to overlay the silicon nitride layer. The silicon oxide layer 705 electrically isolates a conductive gate 702 formed over the second isolating layer 705. The two silicon oxide layers 703 and 705 function as isolation dielectric layers.
The prior art structure shown in FIG. 1 provides a two-bit memory cell, where the cell can store two bits of data. By applying programming voltages to the gate 702 and the drain 701 as the source 700 is grounded, electrons are sufficiently accelerated to be injected into the trapping layer 704 near the drain side 701. The electrons are injected so as to increase the energy barrier in the channel 707 near the drain side 701 where a bit of data is stored therein. Electrons can also be injected into the trapping layer 704 near the source side 702 to increase the energy barrier in the channel 707 near the source side 701 where another bit of data is stored therein. With an appropriate width for the trapping layer 704, the two areas or regions storing electrons in the trapping layer 704 can be accordingly identified and used for storing two bits of data. When no charge is stored in the trapping layer, the energy barrier in the channel 707 is in a low threshold voltage state. The memory cell is utilized in storing data by erasing it to a low threshold voltage state and programming to a high threshold voltage state. In programming the nonvolatile memory cell, the electrons are injected into the trapping layer near, e.g., the drain 701, so that the energy barrier in the channel 707 near the drain 701 is increased. When the electrons are injected into the trapping layer 704 near the source 700, the energy barrier in the channel 707 near the source 700 is increased. The energy barrier in the channel 707 thus includes two high-level sections distributed at two sides of the energy barrier.
The nonvolatile memory cell involves the trapping of electron charges in a trapping layer therein. The trapping layer is generally in a neutral state. When no charges are stored in the trapping layer, the energy barrier is in a low threshold voltage state. In operating the nonvolatile memory cell, the electrons are injected into the trapping layer so that the energy barrier in the channel is increased. As the nonvolatile memory cell is repeatedly operated for a plurality of program/erase cycles, damages are done to the energy barrier of the isolating layer. Some of the trapped storage electrons in shallow traps in the trapping layer will escape through damaged spots, which result in data loss and retention failures. Such adverse effects are significant design and implementation shortcomings in prior art nonvolatile memory devices. Furthermore, prior art nonvolatile memory structures requires a particularly confined size, which impedes engineering efforts on size and cost reduction therefor.
Thus, there is a general need in the art for a nonvolatile memory device with an optimal two-bit cell structure, and more particularly, a nonvolatile memory device and associated methods therefor that overcome at least the aforementioned disadvantages of nonvolatile memory devices in the art. In particular, a need exists in the art for an optimally designed nonvolatile memory device and methods therefor that advantageously prevent data loss in its trapping layer.
The invention advantageously provides a nonvolatile memory device and associated methods therefore, and, more particularly, an optimally designed nonvolatile memory device and methods therefor that advantageously prevent data loss in its trapping layer. Various embodiments of the invention are applicable to a plurality of nonvolatile memory devices, including read only memory (ROM), flash memory, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash EEPROM, and, more particularly, silicon oxide-silicon nitride-silicon oxide (SONOS) nonvolatile memory and floating gate nonvolatile memory.
A preferred embodiment of the method for operating a nonvolatile memory cell according to the invention advantageously comprises the steps of programming the memory cell, injecting electrons into a trapping layer of the memory cell from a semiconductor substrate, erasing the memory cell, detrapping the memory cell, and repeating the erasing and detrapping steps until a threshold voltage of the memory cell reaches a predetermined value. For the detrapping step, electrons can be detrapped from the trapping layer to a channel region of the memory cell, or to a gate of the memory cell. The method according to the invention can further include the steps of verifying the state of the trapping layer and the memory cell (high or low threshold voltage), and repeating the erasing and detrapping steps if the state of the trapping layer and the memory cell are not verified.
Another preferred embodiment of the method for operating a nonvolatile memory cell according to the invention advantageously comprises the steps of programming the memory cell, injecting electrons into a trapping layer of the memory cell from a semiconductor substrate, erasing the memory cell, detrapping the memory cell using electrical field induced ejection, and repeating the erasing and detrapping steps until a threshold voltage of the memory cell reaches a predetermined value.
Another embodiment of the method for operating a nonvolatile memory cell according to the invention advantageously comprises the steps of programming the memory cell, injecting electrons into a trapping layer of the memory cell from a semiconductor substrate using hot electron injection, erasing the memory cell, detrapping the memory cell, and repeating the erasing and detrapping steps until a threshold voltage of the memory cell reaches a predetermined value. The detrapping step in the method according to this particular embodiment of the invention can be performed using electrical field induced ejection.
A preferred embodiment of a nonvolatile memory cell according to the invention advantageously comprises a semiconductor substrate, a drain, a source, a gate, a channel formed between the drain and the source, a first isolating layer above the channel, a trapping layer above the first isolating layer, a second isolating layer above the trapping layer, means for programming the memory cell, means for injecting electrons into the trapping layer from the semiconductor substrate, means for erasing the memory cell, and means for detrapping the memory cell. The erasing and detrapping of the memory cell are repeatedly performed until a threshold voltage of the memory cell reaches a predetermined value. For the detrapping of the memory cell, electrons can be detrapped from the trapping layer to the channel of the memory cell, or to the gate of the memory cell. The state of the trapping layer and the memory cell (high or low threshold voltage) can also be verified, where the erasing and detrapping of the memory cell are repeatedly performed if the state of the trapping layer and the memory cell are not verified.